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INTEGRATED CIRCUITS
DATA SHEET
TDA9150B Programmable deflection controller
Preliminary specification File under Integrated Circuits, IC02 July 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Programmable deflection controller
FEATURES General * 6.75, 13.5 and 27 MHz clock frequency * Few external components * Synchronous logic * I2C-bus controlled * Easy interfacing * Low power * ESD protection * Flash detection with restart * Two-level sandcastle pulse. Vertical deflection * Self adaptive 16-bit precision vertical scan * DC coupled deflection to prevent picture bounce * Programmable fixed compression to 75% * S-correction can be preset * S-correction setting independent of the field frequency * Differential output for high DC stability * Current source outputs for high EMC immunity * Programmable de-interlace phase. East-West correction * DC coupled EW correction to prevent picture bounce * 2nd and 4th order geometry correction can be preset * Trapezium correction * Geometry correction settings are independent of field frequency * Self adaptive Bult generator prevents ringing of the horizontal deflection * Current source output for high EMC immunity. ORDERING INFORMATION PACKAGE TYPE NUMBER PINS TDA9150B 20 PIN POSITION DIP MATERIAL plastic Horizontal deflection * Phase 2 loop with low jitter * Internal loop filter * Dual slicer horizontal flyback input * Soft start by I2C-bus
TDA9150B
* Over voltage protection/detection with selection and status bit. EHT correction * Input selection between aquadag or EHT bleeder * Internal filter. GENERAL DESCRIPTION The TDA9150B is a programmable deflection controller contained in a 20-pin DIP package and constructed using BIMOS technology. This high performance synchronization and DC deflection processor has been especially designed for use in both digital and analog based TV receivers and monitors, and serves horizontal and vertical deflection functions for all TV standards. The TDA9150B uses a line-locked clock at 6.75, 13.5 or 27 MHz, depending on the line frequency and application, and requires only a few external components. The device is self-adaptive for a number of functions and is fully programmable via the I2C-bus.
CODE SOT146-1
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
QUICK REFERENCE DATA SYMBOL VCC ICC Ptot Tamb Inputs V14 V13 V12 V5 V18 V17 VPSL V1 V3 V9 Outputs V20 I11-I10(M) V10,11 I6(M) V6 V2 V2 V2 V19 Notes 1. Hard wired to ground or VCC is highly recommended. 2. DAC values: vertical amplitude = 31; EHT = 0; SHIFT = 3; SCOR = 0. horizontal output (HOUT) voltage (open drain) vertical differential (VOUTA, B) output current (peak value) vertical output voltage EW (EWOUT) total output current I8 = -120 A (peak value) EW (EWOUT) output voltage I20 = 10 mA vertical amplitude = 100%; I8 = -120 A; note 2 - 440 0 - 1.0 - - - I19 = 2 mA 0 - 475 - - - 0.5 2.5 4.5 - line-locked clock (LLC) logic level horizontal sync (HA) logic level vertical sync (VA) logic level line-locked clock select (LLCS) logic level serial clock (SCL) logic level serial data input (SDA) logic level horizontal flyback (HFB) phase slicing level horizontal flyback (HFB) blanking slicing level over voltage protection (PROT) level EHT flash detection level FBL = logic 0 FBL = logic 1 note 1 - - - - - - - - - - - TTL TTL TTL CMOS 5 V CMOS 5 V CMOS 5 V 3.9 1.3 100 3.9 1.5 PARAMETER supply voltage supply current total power dissipation operating ambient temperature fclk = 6.75 MHz CONDITIONS - - -25 MIN. 7.2 8.0 27 220 - TYP.
TDA9150B
MAX. 8.8 - - +70 - - - - - - - - - - -
UNIT V mA mW C
V V mV V V
0.5 510 3.9 930 5.5 - - - VCC
V A V A V
SANDCASTLE OUTPUT LEVELS (DSC) base voltage level horizontal and vertical blanking voltage level video clamping voltage level V V V
HORIZONTAL OFF-CENTRE SHIFT (OFCS) output voltage V
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
BLOCK DIAGRAM
TDA9150B
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
PINNING SYMBOL HFB DSC PROT AGND LLCS EWOUT EHT RCONV FLASH VOUTB VOUTA VA HA LLC DGND VCC SDA SCL OFCS HOUT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION horizontal flyback input display sandcastle input/output over voltage protection input analog ground line-locked clock selection input east-west geometry output EHT compensation external resistive conversion flash detection input vertical output B vertical output A vertical information input horizontal information input line-locked clock input digital ground supply input (+8 V) serial data input/output serial clock input off-centre shift output horizontal output
TDA9150B
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION Input signals (pins 12, 13, 14, 17 and 18) The TDA9150B requires three signals for minimum operation (apart from the supply). These signals are the line-locked clock (LLC) and the two I2C-bus signals (SDA and SCL). Without the LLC the device will not operate because the internal synchronous logic uses the LLC as the system clock. I2C-bus transmissions are required to enable the device to perform its required tasks. Once started the IC will use the HA and/or VA inputs for synchronization. If the LLC is not present the outputs will be switched off and all operations
discarded (if the LLC is not present the line drive will be inhibited within 2 s, the EW output current will drop to zero and the vertical output current will drop to 20% of the adjusted value within 100 s). The SDA and SCL inputs meet the I2C-bus specification, the other three inputs are TTL compatible. The LLC frequency can be divided-by-two internally by connecting LLCS (pin 5) to ground thereby enabling the prescaler. The LLC timing is given in the Chapter "Characteristics".
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
I2C-bus commands Slave address: 8C HEX = 1000110X BIN
READ MODE
TDA9150B
* Logic 0: - after a successful read of the status byte. PROT is the over voltage detection for the scaled EHT input: * Logic 1: - if the scaled EHT rises above the reference value of 3.9 V * Logic 0: - after a successful read of the status byte and EHT <3.9 V. Remark: a read action is considered successful when an End Of Data signal has been detected (i.e. no master acknowledge).
The format of the status byte is: PON PROT 0 0 0 0 0 0 Where: PON is the status bit for power-on reset (POR) and after power failure: * Logic 1: - after the first POR and after power failure; also set to 1 after a severe voltage dip that may have disturbed the various settings - POR 1 to 0 transition, VCC = 6.25 V (typ.) - POR 0 to 1 transition, VCC = 5.75 V (typ.)
Table 1 Write mode with auto increment; subaddress and data byte format. DATA BYTE FUNCTION Vertical amplitude Vertical S-correction Vertical start scan Vertical off-centre shift EW trapezium correction EW width/width ratio EW parabola/width ratio EW corner/parabola ratio EHT compensation Horizontal phase Horizontal off-centre shift Clamp shift Control 1 Control 2 Notes 1. X = don't care. 2. Data bit used in another function. SUBADDRESS D7 00 01 02 03 03 04 05 06 07 08 09 0A 0B 0F X(1) X X X X X X X X X X X MS X D6 X X X note 2 A6 X X X X X X X WS X D5 A5 A5 A5 note 2 A5 A5 A5 A5 A5 A5 A5 X FBL X D4 A4 A4 A4 note 2 A4 A4 A4 A4 A4 A4 A4 X VAP VPR D3 A3 A3 A3 X X A3 A3 A3 A3 A3 A3 X BLDS CPR D2 A2 A2 A2 A2 note 2 A2 A2 A2 A2 A2 A2 A2 LFSS DIP D1 A1 A1 A1 A1 note 2 A1 A1 A1 A1 A1 A1 A1 DINT PRD D0 A0 A0 A0 A0 note 2 A0 A0 A0 A0 A0 A0 A0 GBS CSU
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
Table 2 Control bits. CONTROL BIT LFSS LOGIC 0 1 DINT 0 1 BLDS GBS VAP FBL CSU 0 1 0 1 0 1 0 1 0 1 PRD DIP CPR 0 1 0 1 0 1 VPR 0 1 FUNCTION
TDA9150B
Line stop: EW output current becomes zero and the vertical output current is reduced to 20% of the adjusted value. LFSS becomes logic 0 after a HIGH on PON. Line start enabled: the soft start mechanism is now activated. De-interlace on: the VA pulse is sampled at a position selected with control bit DIP. De-interlace off: the VA pulse is sampled with the system clock and the detected rising edge is used as vertical reset. Aquadag selected. Bleeder selected. Becomes logic 0 after power-on. Guard band 48/12 lines. Positive VA edge detection. Negative VA edge detection. Horizontal flyback slicing level = 3.9 V. Horizontal flyback slicing level = 1.3 V. No clamping suppression, standard mode of operation. Clamping suppression in wait, stop and protection modes (used in systems with e.g. TDA4680/81). No defeat of HOUT, the over voltage information is only written in the PROT status bit. HOUT is defeated and status bit PROT is set when over voltage is detected. VA is sampled 42 clock pulses after the leading edge of HA. VA is sampled 258 clock pulses after the leading edge of HA. Nominal amplitude. Compression to 75% of adjusted amplitude, used for display of 16 : 9 standard pictures on 4 : 3 displays. Nominal amplitude (100%) during wait, stop and clipping. Amplitude reduced to 20% during wait, stop and clipping.
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
Table 3 Explanation of control bits shown in Table 2. CONTROL BITS LFSS DINT BLDS GBS VAP FBL CSU PRD DIP CPR VPR line frame start/stop de-interlace bleeder mode selection guard band selection polarity of VA edge detection flyback slicing level clamping suppression mode protection/detection mode de-interlace phase compression on/off vertical power reduction mode DESCRIPTION
TDA9150B
Table 4 Clock frequency control bit (pin 5; note 1). CONTROL BIT LLCS LOGIC 0 1 Note 1. Switching of the prescaler is only allowed when LFSS is LOW. It is highly recommended to hard wire LLCS to ground or VCC. Active switching may damage the output power transistor due to the changing HOUT pulse. This may cause very high currents and large flyback pulses. The permitted combinations of LLC and the prescaler are shown in Table 5. Table 5 Line duration with prescaler. LLC (MHz) 6.75 13.5 27 Note 1. Combination not allowed. ON (s) note 1 64 32 OFF (s) 64 32 note 1 FUNCTION prescaler on: the internal clock frequency fclk = 12fLLC prescaler off (default by internal pull-up resistor): the internal clock frequency fclk = fLLC
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Preliminary specification
Programmable deflection controller
TDA9150B
Fig.3 Timing relations between LLC, HA and line counter. July 1994 9
Philips Semiconductors
Preliminary specification
Programmable deflection controller
Horizontal part (pins 1, 2, 13, 19 and 20) SYNCHRONIZATION PULSE The HA input (pin 13) is a TTL-compatible CMOS input. Pulses on this input have to fulfil the timing requirements as illustrated in Fig.6. For correct detection the minimum pulse width for both the HIGH and LOW periods is 2 internal clock periods. FLYBACK INPUT PULSE The HFB input (pin 1) is a CMOS input. The delay of the centre of the flyback pulse to the leading edge of the HA pulse can be set via the I2C-bus with the horizontal phase byte (subaddress 08), as illustrated in Fig.7. The resolution is 6-bit. OUTPUT PULSE The HOUT pulse (pin 20) is an open-drain NMOS output. The duty factor for this output is typically 5248 (conducting/non-conducting) during normal operation. A soft start causes the duty factor to increase linearly from 5 to 52% over a minimum period of 2000 lines in 2000 steps. OFF-CENTRE SHIFT The OFCS output (pin 19) is a push-pull CMOS output which is driven by a pulse-width modulated DAC. By using a suitable interface, the output signal can be used for off-centre shift correction in the horizontal output stage. This correction is required for HDTV tubes with a 16 x 9 aspect ratio and is useful for high performance flat square tubes to obtain the required horizontal linearity. For applications where off-centre correction is not required, the output can be used as an auxiliary DAC. The OFCS signal is phase-locked with the line frequency. The off-centre shift can be set via the I2C-bus, subaddress 09, with a 6-bit resolution as illustrated in Fig.8. SANDCASTLE The DSC input/output (pin 2) acts as a sandcastle generating output and a guard sensing input. As an output it provides 2 levels (apart from the base level), one for the horizontal and vertical blanking and the other for the video clamping. As an input it acts as a current sensor during the vertical blanking interval for guard detection. CLAMPING PULSE
TDA9150B
The clamping pulse width is 21 internal clock periods. The shift, with respect to HA can be varied from 35 to 49 clock periods in 7 steps via the I2C-bus, clamp shift byte subaddress 0A, as illustrated in Fig.9. It is possible to suppress the clamping pulse during wait, stop and protection modes with control bit CSU. This will avoid unwanted reset of the TDA4680/81 (only used in those circuits). HORIZONTAL BLANKING The start of the horizontal blanking pulse is minimum 38 and maximum 41 clock periods before the centre of the flyback pulse, depending on the fclk/fH ratio K in accordance with 41 - (432 - K). Stop of the horizontal blanking pulse is determined by the trailing edge of the HFB pulse at the horizontal blanking slicing level crossing as illustrated in Fig.10. VERTICAL BLANKING The vertical blanking pulse starts two internal clock pulses after the rising edge of the VA pulse. During this interval a small guard pulse, generated during flyback by the vertical power output stage, must be inserted. Stop vertical blanking is effected at the end of the blanking interval only when the guard pulse is present (see Section "Vertical guard"). The start scan setting determines the end of vertical blanking with a 6-bit resolution in steps of one line via the I2C-bus subaddress 02 (see Figs 11 and 12). VERTICAL GUARD In the vertical blanking interval a small unblanking pulse is inserted. This pulse must be filled-in by a blanking pulse or guard pulse from the vertical power output stage which was generated during the flyback period. In this condition the sandcastle output acts as guard detection input and requires a minimum 800 A input current. This current is sensed during the unblanking period. Vertical blanking is only stopped at the end of the blanking interval when the inserted pulse is present. In this way the picture tube is protected against damage in the event of missing or malfunctioning vertical deflection (see Figs 11 and 12).
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
Vertical part (pins 6, 8, 10, 11 and 12) SYNCHRONIZATION PULSE The VA input (pin 12) is a TTL-compatible CMOS input. Pulses at this input have to fulfil the timing requirements as illustrated in Fig.6. For correct detection the minimum pulse width for both the HIGH and LOW period is 2 internal clock periods. For further requirements on minimum pulse width see also Section "De-interlace". VERTICAL PLACE GENERATOR With control bit CPR a compress to 75% of the adjusted values is possible in all modes of operation. This control bit is used to display 16 : 9 standard pictures on 4 : 3 displays. No new adjustment of other corrections, such as corner and S-correction, is required. With control bit VPR a reduction of the current during clipping, wait and stop modes to 20% of the nominal value can be selected, which will reduce the dissipation in the vertical drive circuits. The vertical start-scan data (subaddress 02) determines the vertical placement in the total range of 64 x 432 clock periods in 63 steps. The maximum number of synchronized lines per scan is 910 with an equivalent field frequency of 17.2 or 34.4 Hz for fH = 15625 or 31250 Hz respectively. The minimum number of synchronized lines per scan is 200 with an equivalent field frequency of 78 or 156 Hz for fH = 15 625 or 31250 Hz respectively. If the VA pulse is not present, the number of lines per scan will increase to 910.2. If the LLC is not present the vertical blanking will start within 2 s. Amplitude control is automatic, with a settling time of 1 to 2 new fields and an accuracy of either 16/12 or 48/12 lines depending on the value of the GBS bit. Differences in the number of lines per field, as can occur in TXT or in multi-head VTR, will not affect the amplitude setting providing the differences are less than the value selected with GBS. This is called amplitude control guardband. The difference sequence and the difference sequence length are not important. DE-INTERLACE
TDA9150B
With de-interlace on (DINT = logic 0), the VA pulse is sampled with LLC at a position supplied by control bit DIP (de-interlace phase). When DIP = logic 0 sampling takes place 42 clock pulses after the leading edge of HA (T = Tline x 42/432). When DIP = logic 1 sampling takes place 258 clock pulses after the leading edge of HA (T = Tline x 258/432). The distance between the two selectable sampling points is (Tline x (258 - 42)/432) which is exactly half a line, thus de-interlace is possible in two directions. The duration of the VA pulse must, therefore, be sufficient to enable the HA pulse to caught, in this event an active time of minimum of half a line (see Fig.13 which has an integration time of Tline x 14 for the VA pulse). With de-interlace off, the VA pulse is sampled with the system clock. The leading edge is detected and used as the vertical reset. Selection of the positive or negative leading edge is achieved by the control bit VAP. VERTICAL GEOMETRY PROCESSING The vertical geometry processing is DC-coupled and therefore independent of field frequency. The external resistive conversion (RCONV) at pin 8 sets the reference current for both the vertical and EW geometry processing. A useful range is 100 to 150 A, the recommended value is 120 A.
VERTICAL OUTPUTS
The vertical outputs VOUTA and VOUTB on pins 10 and 11 together form a differential current output. The vertical amplitude can be varied over the range 80 to 120% in 63 steps via the I2C-bus (subaddress 00). Vertical S-correction is also applied to these outputs and can be set from 0 to 16% by subaddress 01 with a 6-bit resolution. The vertical off-centre shift (OFCS) shifts the vertical deflection current zero crossing with respect to the EW parabola bottom. The control range is -1.5 to +1.5% (18 x I8) in 7 steps set by the least significant nibble at subaddress 03.
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
EW GEOMETRY PROCESSING The EW geometry processing is DC coupled and therefore independent of field frequency. RCONV sets the reference current for both the vertical and EW geometry processing. The EW output is an ESD-protected single-ended current output. The EW width/width ratio can be set from 100 to 80% in 63 steps via subaddress 04 and the EW parabola/width ratio from 0 to 20% via subaddress 05. The EW corner/EW parabola ratio has a control range of -40 to 0% in 63 steps via subaddress 06. The EW trapezium correction can be set from -1.5 to +1.5% in 7 steps via the most significant nibble at subaddress 03.
BULT GENERATOR
TDA9150B
Flash detection/protection input (pin 9) The FLASH input is a CMOS input with an internal pull-up current of approximately 8 A. When a negative-going edge crosses the 0.75 V level a restart will be executed with a soft start of approximately 2000 lines, such as in the soft-start mode. When the function is not used pin 9 can be connected to ground, VCC or left open-circuit, the internal pull-up current source will prevent any problems. However a hard wired connection to VCC or ground is recommended when the function is not used. EHT compensation (pin 7) The EHT input is a CMOS input. The EHT compensation input permits scan amplitude modulation should the EHT supply not be perfect. For correct tracking of the vertical and horizontal deflection the gain of the EW output stage, provided by the ratio RCONV-EW/RCONV, must be 116Vscan x Vref (see Fig.14). The input for EHT compensation can be derived from an EHT bleeder or from the picture tubes aquadag (subaddress 0B, bit BLDS). EHT compensation can be set via subaddress 07 in 63 steps allowing a scan modulation range from -10 to +9.7%.
The Bult generator makes the EW waveform continuous (see Fig.20). Protection input (pin 3) The protection input (PROT) is a CMOS input. The input voltage must be EHT scaled and has the following characteristics: Two modes of protection are available with the aid of control bit PRD. * With PRD = logic 1 the protection mode is selected, HOUT will be defeated and the PROT bit in the status word is set if the input voltage is above 3.9 V. Thus the deflection stops and EW output current is zero, while the vertical output current is reduced to 20% of the adjusted value. A new start of the circuit is I2C-bus controlled with the user software. * With PRD = logic 0 the detection mode is selected, HOUT will not be defeated and the over voltage information is only written in the PROT status bit and can be read by the I2C-bus. All further actions, such as a write of the LFSS bit, are achieved by the I2C-bus. They depend on the configuration used and are defined by user software.
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Preliminary specification
TDA9150B
Fig.4 Internal circuitry.
handbook, full pagewidth
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17 16 15 14 13 12 11 300 300 300 300
Philips Semiconductors
INTERNAL CIRCUITRY
20
19
18
Programmable deflection controller
300
TDA9150B
13
300 300 300 300 3 45 6 7 8 9 10
MBD863
300
1
2
Preliminary specification
TDA9150B
Fig.5 Application diagram.
handbook, full pagewidth
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10 R105 3 k 9 flash detection input 39 k 8 3 R87 4.7 k IE5 IE5 R117 EHT R88 6 5 100 F 100 nF C105 16 V (vert) 4 R113 7 2 1
Philips Semiconductors
11
APPLICATION INFORMATION
VA
12
HA
13
LLC
14
15
C95 5 C97 100 nF 7 TDA8350 1 R113 330 2 3 45 V (vert) C105 100 F 9 R84 3.3 k 1 R85 15 k 82 k 11 DSC R107 12 Zener diode C110 100 nF 13
MBD864
C89 VCC ( 8 V) 6
Programmable deflection controller
VCC ( 8 V) 4 3.3 k 3 8 R99 2
22 F
100 nF
TDA9150B
16
100
SDA
17
14
10 HFB 23 V (peak)
R75 100
SCL
18
R76
19
LV vertical deflection coil
VCC ( 8 V)
1 k
20
R77
EW-OUT 33 V
HOUT
OFCS
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TIMING DIAGRAMS
TDA9150B
Fig.6 Timing requirements for LLC, HA and VA.
Fig.7 Horizontal phase and HOUT control range.
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NNNNNNN NNNNNNN
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9150B
Fig.8 OFCS duty factor.
Fig.9 DSC clamping pulse.
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9150B
Fig.10 DSC line blanking.
Fig.11 DCS vertical blanking with unblanking.
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9150B
Vertical blanking LOW period: during scan, during unblanking. Vertical blanking HIGH period (2.5 V): during STSC. Vertical blanking continuously HIGH: POR = logic 1, LFSS = logic 0, no guard detected.
Fig.12 DSC with guard interval; start scan = 24.
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Preliminary specification
Programmable deflection controller
TDA9150B
I = start VA for DINT = logic 1. D = start VA for DINT = logic 0.
Fig.13 De-interlace timing.
Fig.14 Explanation of RCONV-EW/RCONV ratio. July 1994 19
Philips Semiconductors
Preliminary specification
Programmable deflection controller
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL VCC ICC Ptot Tstg Tamb Vsupply II/O VESD Note 1. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 70 supply voltage supply current total power dissipation storage temperature operating ambient temperature voltage supplied to pins 1 to 3, 5 to 14 and 17 to 20 current in or out of any pin except pins 4, 15 and 16 electrostatic handling for all pins (note 1) PARAMETER MIN. -0.5 -10 - -65 -25 -0.5 -20 -
TDA9150B
MAX. 8.8 +50 500 +150 +70 VCC + 0.5 +20 2000 V
UNIT mA mW C C V mA V
UNIT K/W
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
CHARACTERISTICS VCC = 8 V; Tamb = 25 C; DGND = AGND = 0 V; unless otherwise specified. SYMBOL Supply VCC ICC Ptot Vpor supply voltage supply current total power dissipation power-on reset POR 1-to-0 transition POR 0-to-1 transition SDA and SCL (pins 17 and 18) V17 VIL VIH IIL IIH VOL V18 VIL VIH IIL IIH VIL VIH I14 tr tf 0 1 SDA input voltage LOW level input voltage (pin 17) HIGH level input voltage (pin 17) LOW level input current (pin 17) HIGH level input current (pin 17) SCL input voltage LOW level input voltage (pin 18) HIGH level input voltage (pin 18) LOW level input current (pin 18) HIGH level input current (pin 18) V18 = VSSD V18 = VCC V17 = VSSD V17 = VCC 0 - 3.5 - - - 0 - 3.5 - - - 2.0 V14 = <5.5 V -10 0 0 LLCS = logic 0; at 1.4 V; note 2 LLCS = logic 1; at 1.4 V; note 2 40 25 - - - - - - - - - - - - - - - - 50 50 5.5 1.5 - note 1; fclk = 6.75 MHz 7.2 - - - 5.0 8.0 27 220 6.25 5.75 8.8 - - 7.0 - PARAMETER CONDITIONS MIN. TYP.
TDA9150B
MAX.
UNIT
V mA mW V V
V V V A A V V V V A A
-10 10 0.4 5.5 1.5 - -10 10
LOW level output voltage (pin 17) IIL = 3 mA
Line-locked clock and line-locked clock select (pins 14 and 5) LOW level input voltage (pin 14) HIGH level input voltage (pin 14) input current rise time fall time duty factor duty factor 0.8 - +10
1 t 2 LLC 1 t 2 LLC
V V A
60 75
% %
TIMING (PRESCALER ON; fclk = 12fLLC WHERE fclk = INTERNAL CLOCK) fLLC K line-locked clock frequency line-locked clock frequency ratio between fLLC and fH line-locked clock frequency ratio between fclk and fH H locked H unlocked H locked H unlocked 12.4 856 - 428 - - 864 866 432 433 29.2 865 - 432.5 - MHz
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Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9150B
SYMBOL
PARAMETER
CONDITIONS
MIN. -
TYP.
MAX.
UNIT
TIMING (PRESCALER OFF; fclk = fLLC WHERE fclk = INTERNAL CLOCK) fLLC K line-locked clock frequency line-locked clock frequency ratio between fLLC and fH line-locked clock frequency ratio between fclk and fH V5 VIL VIH IIL IIH LLCS input voltage LOW level input voltage (pin 5) HIGH level input voltage (pin 5) LOW level input current (pin 5) HIGH level input current (pin 5) V5 = VSSD V5 = VCC H locked H unlocked H locked H unlocked 6.2 428 - 428 - 0 - 3.5 - - 15.5 432 - 432 - 8.8 1.5 - -150 100 V V V A A MHz 432 433 432 433 - - - - -
Horizontal part INPUT SIGNALS
HA (pin 13)
VIL VIH I13 tr tf tWH tWL LOW level input voltage HIGH level input voltage input current rise time fall time pulse width HIGH pulse width LOW V13 = 5.5 V - 2.0 -10 0 0 2 x tclk 2 x tclk FBL = logic 0 FBL = logic 1 Vblank I1 CR blanking slicing level input current 3.7 1.1 0 -10 0 - - - - - - - - 3.9 1.3 0.1 - N x tclk 63 0.8 - +10
1 t 2 LLC 1 t 2 LLC
V V A ns ns
- - 4.1 1.5 0.2 +10 N + (432 - K) x tclk - V V V A
HFB (pin 1)
VPSL phase slicing level
Horizontal phase (delay centre flyback pulse to leading edge of HA; where N = horizontal phase data)
control range number of steps OUTPUT SIGNALS
HOUT (pin 20)
V20 VOL I20 output voltage LOW level output voltage input current duty factor I20 = 0 I20 = 10 mA output off normal operation 0 - -10 51 - - - 52 VCC 0.5 +10 53 V V A %
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Preliminary specification
Programmable deflection controller
TDA9150B
SYMBOL
PARAMETER
CONDITIONS - 5
MIN. - - - -
TYP.
MAX.
UNIT
Soft start (duty factor controlled line drive)
tW CR tss CR initial pulse width soft start control range soft start time 5 53 3000 160 - (432 - K) x tclk - - - 10 ps ns/V s/s % % lines
1500
Switch-off time to the centre of the flyback pulse
control range note 3 0
k PSRR
control sensitivity (loop gain) correction factor sigma value of phase jitter power supply rejection ratio note 4 note 5
400 - - - 0 I19 = 2 mA I19 = -2 mA N <54 N 54 - VCC -0.5 1/K - -
1000 0.5 750 - - - - 1 54
Horizontal off-centre shift (pin 19; N = off-centre shift data)
V19 VOL VOH (max) output voltage LOW level output voltage HIGH level output voltage maximum duty factor duty factor number of steps SANDCASTLE (PIN 2) VCC 0.5 - - - V V V % %
(8N + 1)/K 425/K
DSC output voltage
Vclamp Vblank Vbase I2 tr tf tW tclamp video clamping voltage horizontal and vertical blanking voltage level base voltage level output current rise time fall time guard detected 4.0 2.0 0 guard not detected -1.0 0.8 - - - 35 - 38 4.5 2.5 0.5 - - 60 60 21 x tclk (2N + 35) x tclk 7 41 - (432 - K) x tclk 5.0 3.0 1.0 +0.35 2.5 - - - 49 - 41 V V V mA mA ns ns
Clamping pulse (N = clamp pulse shift data)
clamping pulse width clamp pulse shift w.r.t HA number of steps tstart start of horizontal blanking before middle of flyback pulse
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Preliminary specification
Programmable deflection controller
TDA9150B
SYMBOL
PARAMETER
CONDITIONS
MIN. 1 x 432tclk
TYP.
MAX. 64 x 432tclk 64 - - -
UNIT
Vertical blanking width (N = vertical start-scan data)
CR control range K = 432 number of steps (N + 1) x 432tclk - 63
1 -
lines
Guard detection (N = vertical start-scan data)
tstart tstop start interval w.r.t VA stop interval w.r.t VA no wait no wait {48(N+1) +2} - x tclk {96(N+1) +2} - x tclk
Vertical section
INPUT SIGNALS
(PIN 12; VA) - 2.0 V12 <5.5 V -10 0 0 2 x tclk 2 x tclk de-interlace mode de-interlace mode 0.5 x tline 0.5 x tline 1 x 432tclk K = 432 1 - - fH = 15625 Hz fH = 31250 Hz - - - fH = 15625 Hz fH = 31250 Hz GBS = logic 0 GBS = logic 1 - - - - - 1 - - - - - - - - - (N + 1) x 432tclk - 63 910 17.2 34.4 200 78 156 automatic 16/12 48/12 1.5 0.8 - +10
1 t 2 LLC 1 t 2 LLC
VIL VIH I12 tr tf tWH tWL tWH tWL CR
LOW level input voltage HIGH level input voltage input current rise time fall time pulse width HIGH pulse width LOW pulse width HIGH pulse width LOW
V V A
- - - - 64 x 432tclk 64 - - - - - - - - - - 2 lines lines new fields lines/ scan Hz Hz lines/ scan Hz Hz lines
Vertical place generator (N = vertical start-scan data)
control range
number of steps Lmax feq Lmin feq CA CAg maximum number of synchronized lines per scan equivalent field frequency at 910 lines/scan minimum number of synchronized lines per scan equivalent field frequency at 200 lines/scan amplitude control amplitude control guardband settling time
July 1994
24
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9150B
SYMBOL I(M)
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT A
Vertical geometry processing
vertical differential output current between VOUTA and VOUTB (peak value) drift over temperature range amplitude error due to S-correction setting
1 2(I10+I11)
VA = 100%; note 6; 440 I8 = -120 A - - 275 - - 0 0 - adjacent blocks; note 8 non-adjacent blocks; note 8 - -
475
510
D/T
- - 325 - - - - - - -
10-4 2 375 1 10-4 3.9 3.9 1 2.0 3.0
K-1 % A % K-1 V V %/V % %
vertical output signal bias current I8 = -120 A vertical output offset current offset over temperature range vertical output voltage (pin 10) vertical output voltage (pin 11) common mode rejection ratio linearity error note 7
Ios OS/T V10 V11 CMRR LE
Vertical amplitude (N = vertical amplitude data)
CR control range number of steps note 9 81 - note 9 0 - -18I8 - - 63 - 63 - 7 - - 0.15 - 119 - 15 - +18I8 - A % %
Vertical S-correction (N = S-correction data)
CR control range number of steps
Vertical shift
CR control range number of steps EW output (pin 6) V6 I6 RR D/T output voltage output current output ripple rejection output drift over temperature range note 10 I8 = -120 A; note 11 1.0 15 - - 5.5 930 1 5.10-4 V A %/V K-1
EW WIDTH/WIDTH RATIO CR Ieq control range equivalent output current number of steps note 9 100 15 - - - 63 81 440 - % A
July 1994
25
Philips Semiconductors
Preliminary specification
Programmable deflection controller
TDA9150B
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - 63 - - - 63 - 7
TYP.
MAX.
UNIT
EW PARABOLA/WIDTH RATIO CR Ieq control range equivalent output current number of steps EW CORNER/EW PARABOLA RATIO CR Ieq control range equivalent output current number of steps EW TRAPEZIUM CORRECTION EW trapezium/width ratio number of steps EHT input (pin 7) Vref VI VI mscan mGC II reference voltage input voltage w.r.t Vref input voltage w.r.t VCC scan modulation modulation gain control number of steps input current I8 = -120 A RCONV input (pin 8) VO I8 VI V3 II VI V9 H I9 output voltage current range 3.7 -100 3.9 -120 - 3.9 - - 0.75 0.5 -8 4.1 -150 V A BLDS = logic 1 BLDS = logic 0 BLDS = logic 1 BLDS = logic 0 - - -20 0 -10 0 - -100 3.9 VCC 0 - 0 - 63 - - - +20 -2Vref +9.7 1 - +100 nA V V % V % note 9 -1.5 - +1.5 - % notes 9 and 12 width = 100% width = 80% 40 0 0 - 0 200 160 - % A A note 9 width = 100% width = 80% 1 10 10 - 19 430 345 - % A A
PROT input (pin 3) input voltage voltage detection level input current 0 3.7 -10 VCC 4.1 +10 V V A
FLASH detection input (pin 9) input voltage voltage detection level detection level hysteresis detection pull-up current falling edge 0 0.5 0.3 -4 VCC 1.0 0.8 -16 V V V A
July 1994
26
Philips Semiconductors
Preliminary specification
Programmable deflection controller
Notes to the characteristics
TDA9150B
1. For all other frequencies the expected supply current will be as shown in Table 6 (fclk is the internal clock frequency, fLLC is the internal clock frequency applied to pin 14). 2. When the prescaler is on, one in two LLC HIGH periods is omitted. 3. For 16 kHz operation the minimum value of the control range is 5.7 s. With 12tFB = 5.7 s the minimum storage time is 0 and the maximum is 18 s. For 32 kHz operation the minimum value of the control range is 0 s. With 12tFB = 2.85 s the minimum storage time is 0 and the maximum is 9 s. 4. The k factor is defined as the amount of correction of a phase step. Thus with k = 0.5 a 50% correction of the error takes place each line. The resulting step response now becomes kn, with n the line number after the step. 5. The sigma value () of the jitter with respect to LLC at fH = 32 kHz and a storage time of 5 s. Measurement of is carried out during 200 lines in the active scan, the resulting peak-to-peak value is approximately 6. The visible jitter on the screen will be higher than the peak-to-peak jitter, depending on the deflection stage. 6. DAC values: vertical amplitude = 31; EHT = 0; SHIFT = 3; SCOR = 0. 7. Value is a percentage of I10 - I11. 8. The linearity error is measured without S-correction and based on the same measurement principle as used for the screen. Measuring method: divide the output signal I10 - I11 into 22 equal parts, ranging from 1 to 22 inclusive. Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus part 1 and 22 are unused. ak - a ( k + 1) Linearity error for adjacent blocks = ----------------------------a avg a max - a min Linearity error for non-adjacent blocks = ----------------------------a avg Where a = amplitude, ak = amplitude block k and aavg = average amplitude. 9. Minimum available range. 10. Selection of test mode. When the EW output is pulled above VCC - 0.5 V a special test mode is entered in which the prescaler and the clock detector are disabled. 11. DAC values: vertical amplitude = 31; EHT = 0; WIDTH = 0. 12. The value of -40% (typically 46%) corresponds with data 3F (hexadecimal) and implies maximum 4th order compensation. Table 6 Supply current with prescaler on/off. LLC (MHz) 6.75 13.5 27 Note 1. Combination not allowed. ON (mA) note 1 27 42 OFF (mA) 27 38 note 1
July 1994
27
BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB
I11 - I10.
July 1994 TEST AND APPLICATION INFORMATION Philips Semiconductors
Programmable deflection controller
Fig.16 Control range S-correction.
Fig.15 Control range amplitude.
28 Preliminary specification
TDA9150B
BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB
Philips Semiconductors Fig.18 Control range EW corner/EW parabola ratio. Fig.17 Control range EW parabola/width ratio.
July 1994
Programmable deflection controller
29 Preliminary specification
TDA9150B
BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBB
Philips Semiconductors
July 1994
Programmable deflection controller
Fig.20 The BULT makes the EW waveform continuous.
Fig.19 Control range EW width.
30 Preliminary specification
TDA9150B
Philips Semiconductors
Preliminary specification
Programmable deflection controller
PACKAGE OUTLINE
TDA9150B
seating plane
26.92 26.54 3.2 max 4.2 max
8.25 7.80
3.60 3.05 2.0 max 0.53 max 1.73 max
0.51 min 2.54 (9x) 0.254 M 0.38 max 7.62 10.0 8.3
MSA258
20
11 6.40 6.22
1
10
Dimensions in mm.
Fig.21 Plastic dual in-line package; 20 leads (300 mil); DIP20, SOT146-1.
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. July 1994 31
REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s.
Philips Semiconductors
Preliminary specification
Programmable deflection controller
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9150B
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
July 1994
32
Philips Semiconductors
Preliminary specification
Programmable deflection controller
NOTES
TDA9150B
July 1994
33
Philips Semiconductors
Preliminary specification
Programmable deflection controller
NOTES
TDA9150B
July 1994
34
Philips Semiconductors
Preliminary specification
Programmable deflection controller
NOTES
TDA9150B
July 1994
35
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD33 (c) Philips Electronics N.V. 1994
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Printed in The Netherlands
533061/1500/01/pp36 Document order number: Date of release: July 1994 9397 737 80011
Philips Semiconductors

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